`timescale 1 ns / 100 ps

module Counter28bit_tb;

	reg clk;
	reg rst_n;
	wire [27:0] q;

	Counter28bit dut (
		clk,
		rst_n,
		q
	);

	initial clk = 0;
	always #1 clk = ~clk;

	initial begin
		rst_n = 0;
		#2;
		rst_n = 1;

		#10000;
		rst_n = 0;
		#2;
		rst_n = 1;

		#1000000000;
		$stop;
	end

endmodule
